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MITSUBISHI BIPOLAR DIGITAL ICs
New Product
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Description
The M64893AFP/AGP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using Bip process. It contains the prescaler with operating up to1.3GHz,4 band drivers and Op.Amp for direct tuning.
PIN CONFIGURATION (TOP VIEW)
16 15 14 13 12 11 10
CRYSTAL OSCILLATOR ENABLE INPUT DATA INPUT CLOCK INPUT
PRESCALER INPUT GND SUPPLY VOLTAGE 1
fin GND Vcc1 Vcc2 BS4
1 2 3 4 5 6 7 8
Xin ENA DATA CLK
Features
4 integrated PNP band drivers (Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V ) Built-in Op.Amp for direct tuning voltage output (33V) Low power dissipation (Icc=20mA,Vcc1=5V) Built-in prescaler with input amplifier (Fmax=1.3GHz) PLL lock/unlock status display out put (Built-in pull up resistor ) Xtal 4MHz is used to realize 1 type of tuning steps (Division ratio 1/640) Serial data input (3 wire bus ) Built-in Power on reset system
Small Package(16SOP/16SSOP)
SUPPLY VOLTAGE 2
LD/ f test LD/ f test OUTPUT Vcc3 Vtu Vin SUPPLY VOLTAGE 3 TUNING OUTPUT FILTER INPUT
BAND SWITCHING OUTPUTS
BS3 BS2 BS1
9
OUTLINE 16P2S/16P2Z
Application TV,VCR tuners Recommended operating condition Supply voltage range Rated supply voltage
16P2S
LD/ f test
12
16P2Z
Block diagram * * Vcc1=4.5 to 5.5V Vcc2=Vcc1 to 13.2V XIN ENA DATA Vcc3=28 to 35V * * Vcc1=5.0V 16 15 14 Vcc2=12V Vcc3=33V
OSC DIVIDER
CLK
13
Vcc3 Vtu
11 10
Vin
9
19-BIT SHIFT RESISTER LATCH
Vcc1
Function 1/32,1/33 dual-modulus prescaler 4MHz crystal oscillator,reference divider Programmable divider (10-bit M counter,5-bit S counter) Tri-state phase comparator Lock detector Band switch driver Op. Amp for direct tuning
10
10-BIT M COUNTER 1/32,1/33 5-BIT S COUNTER
4
LOCK DETECTOR
5 PHASE DETECTOR CHARGE PUMP
1/8
P.O. reset
Bias
BAND DRIVER
1
2
3
4
5
6
7
8
fIN
GND
Vcc1
Vcc2
BS4
BS3
BS2
BS1
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Pin description
Symbol f in GND Vcc1 Vcc2 BS4 BS3 BS2 BS1 Vin Pin No. 1 2 3 4 5 6 7 8 9 Pin name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0V. Power supply voltage terminal. 5.0 0.5V Power supply for band switching,Vcc1 to 13.2V PNP open collector method is used. When the band switching data is "H",the output is ON. When it is "L",the output is OFF. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output ( f 1/N) is ahead compared to the reference frequency (fref), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. This supplies the tuning voltage. Power supply voltage for tuning voltage 28 to 35V When 19 bit data is input,lock detector is output. When 27 bit data is input, lock detector is output, the programmable freq. Divider output and reference freq. Output is selected by the test mode. Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. This is normally at a "L". When this is at "H", data and clock signals are received. Data is read into the latch when the 19th pulse of the clock signal falls. 4.0MHz crystal oscillator is connected.
Filter input (Charge pump output)
Vtu Vcc3 LD/ f test
10 11 12
Tuning output Power supply voltage 3 Lock detect/ Test port
CLOCK DATA ENABLE
13 14 15
Clock input Data input Enable input
X in
16
This is connected to the crystal oscillator.
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Method of setting data
The frequency demultiplying ratio uses 15bits. Setting up the band switching output uses 4bits. The test mode data uses 8bits. The total bits used is 27bits.Data is read in when the enable signal is "H" and the clock signal falls. The band switching data is read in at the 4th pulse of the clock signal.The program counter data is read into the latch by the fall of the 19th pulse of the clock signal. When the enable signal goes to "L" before the 19th pulse of the enable signal, only the band SW data is updated and other data is ignored. The data is latched at the 19th pulse of the clock signal. At this time, 1/640 frequency division ratio is used. Clock signals after the above are invalid.
ENA DATA CLK
BAND SW DATA M COUNTER DIVISION RATIO SETTING READ INTO LATCH S COUNTER DIVISION RATIO SETTING READ INTO LATCH BS4 BS3 BS2 BS1 29 28 27 M9 M8 M7 26 25 M6 M5 24 23 M4 M3 22 21 M2 M1 20 24 M0 S4 23 22 S3 S2 21 20 S1 S0
How to set the dividing ratio of the programmable divider
Total division N is given by the following formulas in addition to the prescaler used in the previous stage. N=8 * (32M + S) M : 10 bit main counter division S : 5 bit swallow counter division The M and S counters are binary the possible ranges of division are as follows. 32 M 1023 O S 31 Therefore,the range of division N is 8,192 to 262,136. The tuning frequency f VCO is given in the following equations. f VCO= f REF x N =6.25 x 8 x (32M + S) =50.0 x (32M + S) [ kHz ] But,the tuning frequency range is 51.2MHz to 1300Mz from the maximum prescaler operating frequency.
MITSUBISHI
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Test mode data set up method
The data for the test mode uses 20 to 27bits. Data is latched when the 27th clock signal falls. (1) When transferring 3-wire 27 bit data ENA
1
19 20
BAND SW DATA M COUNTER DIVISION RATIO SETTING S COUNTER DIVISION RATIO SETTING
SI CP T2 T1
27
TO RSa RSbOS
CLK
TEST DATA SETTING READ INTO LATCH
(2) Test Mode Bit Set Up X :Random, 0 or 1.normal "0" CP :Set up the charge pump current value T0, T1,&T2 :Set up test modes RSa, Rsa :Set up for the reference Frequency division ratio OS :Set up the tuning amplifier SI :1 Only (It is prohibit to "0 ")
Setting up the charge pump current of the phase comparator
CP 0 1 Charge pump current 70 uA 270 uA Mode Test Normal
Setting up for the test mode
T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge pump Normal operation High impedance Sink Source High impedance High impedance 12 pin output LD LD LD LD fREF f1/N Mode Normal operation Test mode Test mode Test mode Test mode Test mode
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Set up for the reference Frequency division ratio
RSa 1 0 X RSb 1 1 0 Division ratio 1/ 512 1/ 1024 1/ 640
Set up the tuning amplifier
OS 0 1 Tuning voltage out put ON OFF Mode Normal Test
Power on reset operation (Initial state the power is turned ON)
BS4 to BS1 Charge pump Tuning amplifier Charge pump current Frequency division ratio Lock detect : OFF : High impedance : OFF : 270uA : 1/640 :H
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Timing diagram
tr ENABLE
10% 90% 1.5V 90%
tf VIH
10%
tINT
90% 1.5V 10% tr 90% 1.5V 10% 90% tr 10% tf 90%
tINT
VIL VIH VIL VIH VIL
tBT
DATA
10% tf
CLOCK tPWC tSU(D) tSU(E)
tH(D)
tH(E)
tBCL
Crystal oscillator connection diagram
16
Crystal oscillator characteristics Actual resistance : less than 3 0 0 Load capacitance : 2 0 p F
18pF 4MHz
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Absolute maximum ratings (Ta=-20C to +75C unless otherwise noted)
Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage Output voltage Voltage applied when the band output is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature Symbols Vcc1 Vcc2 Vcc3 VI Vo VBSOFF IBSON tBSON Pd Topr Tstg Max.ratings 6.0 14.4 36.0 6.0 6.0 14.4 50.0 10 Units V V V V V V mA sec Conditions Pin3 Pin4 Pin11 Not to exceed Vcc1 LD output
470 mW -20 to +75 C -40 to +125 C
per 1 band output circuit 50mA per 1 band output circuit 3circuits are pn at same time, Ta= +75C
Recommended operating conditions (Ta=-20C to +75Cunless otherwise noted)
Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Symbol Vcc1 Vcc2 Vcc3 fopr1 fopr2 IBDL Ratings 4.5 to 5.5 Vcc1 to 13.2 28 to 35 4.0 80 to 1,300 0 to 40 Units V V V MHz MHz mA Conditions Pin3 Pin4 Pin11 Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time.
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR Electrical characteristics (Ta=-20C to +75C unless otherwise noted) Vcc1=5.0V, Vcc=12V, Vcc3=33V Parameters Input terminals "H"input voltage "L"input voltage "H"input current "L"input current "L"input current Lock output "H"output voltage "L"output voltage Band SW output voltage Leak current Tuning output output voltage "H" output voltage "L" Charge pump "H" output current "L" output current Leak current Supply current 1 Supply current 2 4 circuits OFF 1 circuits ON, Output open Output current 40mA Supply current 3 Symbol Test pin Limits Typ -6 -18 0.3 11.8 0.2 270 70 20 6.0 46.0 3.0
Test conditions Min
Unit Max Vcc1+0.3 1.5 10 -10 -30 0.5 -10 0.4 370 110 50 30 0.3 8.0 48.0 4.0 V V uA uA uA V V V uA V V uA uA nA mA mA mA mA mA
VIH VIL IIH IIL IIL VOH VOL VBS IOlk2 VtoH VtoL ICPH ICPL IcpLK Icc1 Icc2A Icc2B Icc2C Icc3
13 to 15 13 to 15 13 to 15 13,15 14 12 12 5 to 8 5 to 8 10 10 9 9 9 3 4 4 4 11
Vcc1=5.5V ,Vi=4.0V Vcc1=5.5V,Vi=0.4V Vcc1=5.5V ,Vi=0.4V Vcc1=5.5V Vcc1=5.5V Vcc2=12V Io=-40mA Vcc2=12V Band SW is OFF Vcc3=33V Vcc3=33V Vcc1=5.0V Vo=1V Vcc1=5.0V Vo=1V Vcc1=5.0V Vo=2.5V Vcc1=5.5V Vcc2=12V Vcc2=12V Vcc2=12V Io=-40mA Vcc3=33V Output ON
3.0 5.0 11.6 32.5 -
The typical values are at Vcc1=5V,Vcc2=12V,Vcc3=33V,Ta=+25C
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Switching characteristics (Ta=-20C to +75C unless otherwise noted)
Vcc1=5.0V, Vcc2=12V, Vcc3=33V Parameter Prescaler operating frequency Operating input voltage Symbol Test pin 1 f opr2 V in 1 Test conditions Vcc1=4.5 to 5.5V Vin=Vinmin to Vinmax Vcc1=4.5 80 to 100MHz to 5.5V 100 to 200MHz 200 to 800MHz 800 to 1000MHz 1000 to 1300MHz Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Vcc1=4.5 to 5.5V Min. 80 - 24 - 27 - 30 - 27 - 18 1 2 1 3 3 1 5 5 Limits Typ Unit used MHz dBm
Max 1300 4 4 4 4 4 1 1 -
Clock pulse width Data setup time Data hold time Enable setup time Enable hold time Enable data interval time Rise time Fall time Next enable prohibit time Next clock prohibit time
t PWC t SU(D) t H(D) t SU(E) t H(E) t INT tr tf t BT t BCL
13 14 14 15 15 15,14 13,14,15 13,14,15 15 13,15
us us us us us us us us us us
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Application example BUILT-IN PLL TUNER
+5V
1000pF
+ 10 -
Vcc1 to 12V
UHF VHF
3
M64893AFP / AGP
+ -
5
SW
18
Vcc2
47k
4 5 6 7
+B BS4
B S 4 11
47k
4-BAND TUNER
B S 3 12
47k
BS3 IF BS2
B S 2 13
47k
IF
1 MCU
14 13 15 12
TEST
B S 1 14
8
BS1
M5493X series
f IN 17
G N D 16
C 1000 Ce e
1000pF
Lo
3 4 2 20
DATA CLK EN LD
15
0.1u
1.5n
VT
AGC
AGC
10 / f1/N XOUT 7 PD 9
9 10
56K
56K
2.2n
AFT
100P
X IN
+5V 16
*
GND 8
11
+ Note)Filter constant is for reference. Add a capacitor to stabilize the circuit.
6
18p
*
4MHz
+33V
BT
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Marking DWG
(M64893AFP)
893AFP
XXXX
L o t No,
External appearance 16P2S type <16pin plastic mold SOP> Unit:mm
16
9
0.05
1
1.270.15
8
+0.1
+0.05 0.15 -0.02
0.4 -0.05
10.00.2
MITSUBISHI
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Marking DWG
(M64893AGP)
893A XXX
Lot No,
External appearance 16P2Z type <16pin plastic mold SSOP>
16
Unit:mm
9
4.40.1
0.05
1
0.650.12
8
+0.1
0.22 -0.05
5.00.2 1.9 1.5
0.1
MITSUBISHI
0.50.2
+0.05 0.15 -0.02
6.20.2
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